Timeline for Why is division so much more complex than other arithmetic operations?
Current License: CC BY-SA 4.0
15 events
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| S Jun 25, 2020 at 18:05 | history | suggested | CommunityBot | CC BY-SA 4.0 |
Fixed broken link.
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| Jun 25, 2020 at 16:42 | review | Suggested edits | |||
| S Jun 25, 2020 at 18:05 | |||||
| Nov 27, 2018 at 23:32 | comment | added | Peter Cordes | For divps / divpd vs. mulps / mulpd latency and throughput numbers, see Floating point division vs floating point multiplication. I took data from Agner Fog's instruction tables and formatted it into a summary across uarches of div and mul throughput and latency, for single vs. double and for different SIMD vector widths. (Intel chips typically have a SIMD divider that's only half the width of the other vector ALUs.) | |
| Apr 13, 2017 at 12:53 | history | edited | CommunityBot |
replaced http://scicomp.stackexchange.com/ with https://scicomp.stackexchange.com/
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| Mar 14, 2017 at 10:59 | comment | added | Mark Booth | CPU manufacturers would only dedicate a large swath of silicon to a low latency floating point divide unit if they couldn't use that silicon more effectively to speed up the CPU in other ways. Generally speaking though, having more long latency FDIVs are a more efficient use of silicon than fewer shorter latency FDIVs. AS for current generation CPUs, as with other areas, we have only seen incremental improvements. Some division operation latencies apparently dropped from 20 cycles to 14 cycles this generation, but that is quite rare these days. | |
| Jan 11, 2017 at 16:34 | history | edited | Mark Booth | CC BY-SA 3.0 |
Replace broken link with archive.org version. Fix a few typos.
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| Jan 11, 2017 at 13:59 | comment | added | Matthieu M. | I am not sure what the latency of such a division would be, though. At 4 GHz, making a round-trip to the look-up table within N cycles severely limits the potential size of said table (for example, the L1 caches have been stagnating at 32K each). Going 3D would help increasing this (but is challenging wrt. cooling). Do you have any idea what latency could be reached for modern 4GHz/5GHz CPUs? | |
| Dec 10, 2011 at 15:43 | history | edited | Mark Booth | CC BY-SA 3.0 |
added 738 characters in body
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| Dec 10, 2011 at 15:33 | history | edited | Mark Booth | CC BY-SA 3.0 |
added 738 characters in body
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| Dec 7, 2011 at 11:27 | comment | added | Matt Knepley | I think DSPs do that by limiting the range in which they are accurate. This is the same strategy used for lookup+interpolation for square root. | |
| Dec 6, 2011 at 19:48 | comment | added | Mark Booth | @Bill - Thanks, you're right. I'm sure I've seen single-cycle division operations in DSP chips before, so assumed it would have made it's way to the desktop, just as single-cycle multiply did, but I can't find any references now. I've updated my answer and added some relevant information on non iterative methods which might allow it in the future though. It's amazing to think that division is no more efficient per cycle now than back when I was using transputers. | |
| Dec 6, 2011 at 19:44 | history | edited | Mark Booth | CC BY-SA 3.0 |
Added some information on non-iterative methods.
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| Dec 6, 2011 at 15:06 | comment | added | Bill Barth | To my knowledge, no chips have single-cycle divide latencies for floating point. For example, Agner Fog's instruction tables for Intel, AMD, and VIA CPUs lists DIVPS (SSE packed floating-point divide) as 10-14 cycles. I can't find any hardware with single-cycle divide instructions, but I'd be willing to be proved wrong. It's not common as far as I can tell. | |
| Dec 6, 2011 at 14:10 | vote | accept | Phonon | ||
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| Dec 5, 2011 at 13:21 | history | answered | Mark Booth | CC BY-SA 3.0 |