This is a good question because understanding numerical algorithms and performance is an important prerequisite to being an effective computational scientist. At the same time, it is a poor question because the constraints as posed do not sufficiently qualify it to give a meaningful answer.
The performance of the three computations will strongly depend on the accuracy needed in the final result as well as the minimum precision required to represent the operands. You qualify $a$, $b$, and $c$ as positive real numbers, but we also need to know how many binary digits $d_n$ are required to represent them accurately. To understand the performance considerations for general real numbers, we first need to understand how computers represent integers as well as how it approximates real numbers using floating-point numbers.
When computers operate on an integer $M$, then the number of binary digits needed is obviously equal to the log$_2$ of the magnitude of the integer, plus an extra bit for handling the sign:
$d_n=$log$_2|M|+1$
For example, the number -8 can be represented with 4 binary digits. For performance and space-efficiency, arithmetic logic units (ALUs), responsible for numerical computations of integers on modern processing units, are designed to handle math on integers up to some fixed size, the most common these days being d=32 and d=64. Not just x86 processors like in your computer have ALUs, they are a fundamental building block of computer architecture ubiquitous in today's electronic society. If you are familiar with video game consoles, you might remember the Nintendo 64, a video game system named after the size (in bits), the arithmetic logic units on the console's processor were designed to handle.
Integer additions, subtractions, and multiplications on arithmetic logic units are very efficient, and usually require no more than several cycles to compute. Divisions are less performant, and on modern processors can require as many as several dozen cycles. Performance depends on both the architecture of the processing unit (and corresponding implementation of the arithmetic logic unit) and its frequency. Note that a 64-bit processor can usually perform arithmetic on $x$-bit operands at the same speed for $x$ anywhere between 1 and 64.
In general computing, and especially in scientific computing, integer math is unwieldy for many computations, and another representation of numbers is needed, the so-called 'floating-point' representation. Floating-point numbers represent a compromise between the way modern microprocessors work (carting data around in $n$-bit hunks) and the needs of computation by representing numbers on the processor in truncated scientific notation, using a fixed base $b$ (usually $b=2$ or $b=10$) and representing the number using two integers, a mantissa (significand in some circles) $s$, and an exponent $e$. A given number $x$ is then approximately represented as:
$x = s*b^e$
I say approximately because it should be obvious that even simple rationals such as $\frac{1}{3}$ cannot be represented exactly as a floating-point number for the standard bases. The number of digits committed to the significand determine the accuracy of the number, which is relative to its own magnitude. The IEEE 754 standard specifies a number of rules for how floating-point numbers are expected to behave, including the ranges of the significand and mantissa (and corresponding range and precision) for several important values of $d_n$, so that numerical computations are repeatable within some tolerance.
There is quite a bit of subtlety to how floating-point numbers work which I cannot hope to capture in this answer, for a good introduction I recommend "What Every Computer Scientist Should Know About Floating-Point Arithmetic".
A significant amount of intellectual effort over the last 50 years has been invested in improving processor capability to compute arithmetic floating-point operations efficiently. On modern processors, these computations are handled by one or more Floating-point units (FPUs), a more sophisticated version of the arithmetic logic unit designed to perform arithmetic operations on floating-point numbers and usually designed to handle both IEEE 754-specified 32-bit floating-point numbers (often referred to as 'floats') and 64-bit floating-point numbers (often referred to as 'doubles') efficiently. Similar to arithmetic logic units, floating-point units can often compute addition, subtraction, and multiplication in just a few cycles, while division usually requires slightly more.
In most cases, IEEE 754 64-bit floating-point 'doubles' are sufficient for numerical computations, so let us assume that $a$, $b$, and $c$ are each represented as 64-bit doubles, and you are interested in the performance of the three computations as scalar operations on an Intel Nehalem architecture using the x87 floating-point instruction subset, i.e. you are not interested in calculating these operations in a for loop or over a range of data, and you don't want to use the vector extensions. Instruction latency information is collected from Agner Fog's excellent set of instruction reference tables for Intel/AMD architectures.
- $a^b$
- log$_a c$
- $c^\frac{1}{b}$
1 General exponentiation is often implemented with the following identity:
$a^b = \beta^{a\cdot\text{log}_\beta b}$
Where $\beta$ is either $2$ or $e$ (in this case, I use $\beta=2$). Assuming you are willing to throw away some accuracy in the result (the x87 unit does its computations in 80 bits of precision, but this is insufficient for certain ranges of values for $a$ and $b$), this computation can be done with the FYL2X hardware instruction to compute $t=a\cdot\text{log}_2 b$ and the F2XM1 hardware instruction (with some scaling help) to calculate $2^t$. Assuming ~20 cycles for handling the scaling:
FYL2X + F2XM1 + ~20 = 80 + 51 + ~20 = ~151 cycles
2 This can be transformed to two logarithms and a division by the change of basis identity and does not need rescaling for an accurate result.
2*FYL2X + FDIV = 2*80 + (7 to 27) = 167 to 187 cycles
[3] This is equivalent to a division followed by an exponentiation, so [1] plus FDIV, ~175 cycles.